(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing the size of contacts using a retardation layer in the fabrication of integrated circuit devices.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, feature size has been decreasing. As the design rule decreases, the size of contact holes also decreases. Additionally, the aspect ratio of contact holes has become higher. Contact holes typically pass through multiple conductor layer regions, such as word line and bit line regions, as well as their intervening insulation regions. The increased aspect ratio makes it difficult to fabricate contact holes using conventional lithography techniques without misaligning the holes with respect to the existing device structure. Several techniques, such as tapered contacts and self-aligned contacts, have been proposed for future applications. However, the multi-level contact was found to be much more difficult and complicated than single level contacts even with the tapered or self-aligned contact technologies.
FIG. 1 illustrates such a tapered contact technique. Semiconductor device structures such as gate electrodes 18 have been formed on the surface of the semiconductor substrate 10. Conductors 30 and 40 have been formed on various levels overlying the gate electrodes. Multiple insulating layers comprising borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), silicon oxide, or the like, 60 are formed over and under the conductors. A photoresist mask 80 is formed over the top surface of the insulating layers. The opening A in the photoresist mask is smaller than the opening B at the bottom of the contact opening 90. This a tapered contact opening. However, because of the many layers through which the contact opening is to be made, it is very difficult to avoid the conductors 30 and 40 within the layers. A line short may occur at 95 where a conductor is exposed or very nearly exposed. When the contact opening 90 is filled with a conducting material, a short will occur at 95, leading to device failure.
U.S. Pat. No. 5,663,092 to Lee teaches forming a silicon nitride cap on the top and sidewalls of the conductors. The cap etches more slowly than the insulating layers thus preventing the exposure of the conductors in etching a contact opening. U.S. Pat. No. 5,444,021 to Chung et al teaches exposing and etching away a portion of the topmost conductors, forming oxide spacers on the sidewalls of the conductors to narrow the opening, and then continuing the contact hole etch. U.S. Pat. Nos. 5,389,560 to Park, 5,492,850 to Ryou, and 5,482,886 to Park et al all teach methods of partially etching a contact opening, then forming sidewall spacers of polysilicon or oxide to narrow the opening, and then continuing the contact opening etch. U.S. Pat. No. 5,620,917 to Yoon shows a method of making contact openings and capacitors.